-- $Id: $
-- File name:   CLK_DIV.vhd
-- Created:     3/22/2011
-- Author:      Brandon Blaine Gardner
-- Lab Section: 337-06
-- Version:     1.0  Initial Design Entry
-- Description: Divides input clock by 8.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

entity CLK_DIV is
  port(
    RST     : in  std_logic;
    CLK_in  : in  std_logic;
    CLK_48 : out std_logic;
    CLK_24 : out std_logic
  );
end CLK_DIV;

architecture DIV_arch of CLK_DIV is
  
  signal output48, nextout48 : std_logic;
  signal output24, nextout24 : std_logic;
  signal count, nextcount : std_logic_vector(1 downto 0);
  
begin
  
  process( RST, CLK_in )
  begin
    if( RST = '0' )
    then
      count <= "00";
      output48 <= '0';
      output24 <= '1';
    elsif( CLK_in'event and CLK_in = '1' )
    then
      count <= nextcount;
      output48 <= nextout48;
      output24 <= nextout24;
    end if;
  end process;
  
  process( count )
  begin
    
    nextcount <= count;
    nextout48 <= not output48; -- invert every clock edge (divides by 2)
    nextout24 <= output24;
    
    if( count = "01" )
    then
      nextcount <= "00";
    else
      if( count = "00" )
      then
        nextout24 <= not output24; -- invert every other clock edge (divides by 4)
      end if;
      nextcount <= count + 1;
    end if;
    
  end process;
  
  CLK_48 <= output48;
  CLK_24 <= output24;
  
end DIV_arch;
    